1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a ferroelectric memory which stores binary data in a nonvolatile manner by using two different magnitudes of polarizations of a ferroelectric substance on the basis of the fact that spontaneous polarization, one of the properties of a ferroelectric substance, presents a hysteresis characteristic.
2. Description of the Related Art
A ferroelectric memory stores binary data in a nonvolatile manner by using two different magnitudes of polarizations of a ferroelectric substance on the basis of the fact that spontaneous polarization, one of the properties of a ferroelectric substance, presents a hysteresis characteristic. A memory cell in a conventional ferroelectric memory has generally employed the same architecture as that of a DRAM (refer to, for example, Jpn. Pat. Appln. KOKAI Publication No. 2001-143478 or Jpn. Pat. Appln. KOKAI Publication No. 2001-250376). In the conventional ferroelectric memory, a normal dielectric capacitor is replaced with a ferroelectric capacitor and the ferroelectric capacitor is connected in series with a transistor, thereby configuring a memory cell. A plurality of units of this memory cell are arranged, thereby configuring a memory cell array.
In addition to the memory cell array, a spare memory cell array is provided to remedy defective bits in the memory cell array. If a defective bit has occurred in a block in the memory cell array, the block is replaced with a block in the spare memory cell array. This enables the overhead of the chip area to be minimized and the chip yield to be increased.
Furthermore, providing the chip with an error checking and correcting (ECC) circuit makes it possible to correct the error in the data, when there is an error only in one bit in a plurality of items of data read out. The method with the ECC circuit works on a defective bit from which erroneous data will be read at a certain probability under a specific condition, not on a defective bit which can be neither read from nor written to a cell in the memory cell array. Using this method enables the reliability of read data to be improved.
In a case where the chip is provided with both the spare memory cell array and the ECC circuit, when data replacement is needed using the spare memory cell array, the data in the memory cell array is replaced with the data in the spare memory cell array first. Next, using a syndrome computing circuit, syndromes are calculated from the data in the memory cell array and the data in a part of the spare memory cell array. If there is a 1-bit error, the ECC circuit corrects the error on the basis of the syndrome and the read data and outputs the result. A ferroelectric memory is a nonvolatile memory. Since the ferroelectric memory uses a destructive read operation, the series of operations has to be carried out in a short period from when the data is read onto the data line until the data is written again.
Since the spare memory cell array is generally provided adjacent to the memory cell array, some of the blocks in the memory cell are close to the spare memory cell array and some are far away from the spare memory cell array. The difference in wiring length between a block close to and a block far away from the spare memory cell array is large. When the data read from a memory cell in the block far away from the spare memory cell array is replaced with the data in the spare memory cell array, the time required to replace the data in the memory cell array with the data in the spare memory cell array increases. This results in an increase in the cycle time and an increase in the access time.